EM6. 4T IA- 3. 2 LGA7. CK4. 10. B - Datasheet Archive. Dual- Core Intel. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked . Current characterized errata are available on request. Processor will not operate (including 3. Intel EM6. 4T- enabled BIOS. Performance will vary depending on your hardware and software configurations. Intel EM6. 4T- enabled OS, BIOS, device drivers and applications may not be available. Check with your vendor for more information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Xeon, Intel Speed. Step, Intel Extended Memory 6. Intel introduces innovative silicon technology processes, delivering leaps in performance and energy efficiency while enabling richer applications. Dual core technology is two individual microprocessors on a single computer chip. The main advantage of dual core technology is. AMD Technology & Software Justin Boggs. AMD Dual Core provides enhanced performance without.
Technology, Intel Virtualization Technology, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. State of Data . 1. Electrical Specifications . Front Side Bus and GTLREF . Power and Ground Lands. Decoupling Guidelines . VCC Decoupling. 1. VTT Decoupling . 1. Front Side Bus AGTL+ Decoupling . Front Side Bus Clock (BCLK. Front Side Bus Frequency Select Signals (BSEL. PLL Power Supply . Voltage Identification (VID) . Reserved or Unused Signals. Front Side Bus Signal Groups . CMOS Asynchronous and Open Drain Asynchronous Signals . Test Access Port (TAP) Connection. Platform Environmental Control Interface (PECI) DC Specifications. DC Characteristics . Input Device Hysteresis . Mixing Processors. Absolute Maximum and Minimum Ratings . Processor DC Specifications . VCC Overshoot Specification . Die Voltage Validation . Mechanical Specifications. Package Mechanical Drawings . Processor Component Keepout Zones. Package Loading Specifications . Package Handling Guidelines. Package Insertion Specifications. Processor Mass Specifications . Processor Materials. Processor Land Coordinates . Dual- Core Intel. Land Listing by Land Name . Land Listing by Land Number . Signal Definitions . Signal Definitions . Thermal Specifications . Package Thermal Specifications . Thermal Specifications . Thermal Metrology . Processor Thermal Features . Thermal Monitor Features. Dual- Core Intel. Boxed Processor Retention Mechanism and Heat Sink Support (CEK). Electrical Requirements . Fan Power Supply (Active CEK). Boxed Processor Cooling Requirements. Boxed Processor Contents. Debug Tools Specifications . Debug Port System Requirements . Target System Implementation. System Implementation. Logic Analyzer Interface (LAI) . Mechanical Considerations . Electrical Considerations . Input Device Hysteresis . Dual- Core Intel. Dual- Core Intel. Dual- Core Intel. Case Temperature (TCASE) Measurement Location . Thermal Monitor 2 Frequency and Voltage Ordering . PECI Topology . 8. Temperature Data Format Comparison: Thermal Diode vs. PECI Digital Thermal Sensor. Stop Clock State Machine . Boxed Dual- Core Intel. Boxed Dual- Core Intel. U Passive Dual- Core Intel. Top Side Board Keepout Zones (Part 1) . Top Side Board Keepout Zones (Part 2) . Bottom Side Board Keepout Zones. Board Mounting- Hole Keepout Zones . Volumetric Height Keep- Ins . Pin Fan Cable Connector (For Active CEK Heat Sink) . Pin Base Board Fan Header (For Active CEK Heat Sink). Fan Cable Connector Pin Out for 4- Pin Active CEK Thermal Solution . Table 1- 1 2- 1 2- 2 2- 3 2- 4 2- 5 2- 6 2- 7 2- 8 2- 9 2- 1. Dual- Core Intel. Core Frequency to FSB Multiplier Configuration . Voltage Identification Definition. Voltage Identification Definition. Loadline Selection Truth Table for LL. Market Segment Selection Truth Table for MS. AGTL+ Signal Description Table. Non AGTL+ Signal Description Table . Signal Reference Voltages . PECI DC Electrical Limits . Processor Absolute Maximum Ratings. Voltage and Current Specifications. VCC Static and Transient Tolerance . AGTL+ Signal Group DC Specifications . CMOS Signal Group and TAP Signal Group DC Specifications . Open Drain Signal Group DC Specifications . VCC Overshoot Specifications. Package Loading Specifications . Package Handling Guidelines. Processor Materials. Land Listing by Land Name . Land Listing by Land Number . Signal Definitions . Fan Specifications for 4- Pin Active CEK Thermal Solution. Fan Cable Connector Pin Out for 4- Pin Active CEK Thermal Solution. Dual- Core Intel. Description Date June 2. November 2. 00. 6 August 2. These processors are based on Intel's 6. Some key features include on- die, 3. KB Level 1 instruction and data caches and 4 MB Level 2 cache with Advanced Transfer Cache Architecture. The processors' Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. The 1. 33. 3 MHz Front Side Bus (FSB) is a quad- pumped bus running off a 3. MHz system clock making 1. GBytes per second data transfer rates possible. Some lower speed SKU's are available which support a 1. MHz Front Side Bus (FSB). This is a quad- pumped bus running off a 2. MHz system clock making 8. GBytes per second data transfer rates possible. Enhanced thermal and power management capabilities are implemented including Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel Speed. Step. These technologies are targeted for dual processor in enterprise environments. TM1 and TM2 provide efficient and effective cooling in high temperature situations. Enhanced Intel Speed. Step. Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi- media units include 1. SSE3 instructions provide highly efficient double- precision floating point, SIMD integer, and memory management operations. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 6. Further details on Intel Extended Memory 6. Technology and its programming model can be found in the 6. Extension Technology Software Developer's Guide at http: //developer. In addition, the Dual- Core Intel. When used in conjunction with a supporting operating system, Execute Disable allows memory to be marked as executable or non executable. This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. Further details on Execute Disable can be found at http: //www. Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine Dual- Core Intel. Further details on Intel Virtualization Technology can be found at http: // developer. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. It utilizes a surface mount LGA7. LGA7. 71 socket that supports Direct Socket Loading (DSL). FSB termination voltage (VTT) is shared and must connect to all FSB agents. The processor core voltage utilizes power delivery guidelines specified by VRM/EVRD 1. Voltage Regulator Module (VRM) and Enterprise Voltage Regulator- Down (EVRD) 1. Design Guidelines for further details). VRM/EVRD 1. 1. 0 will support the power requirements of all frequencies of the Dual- Core Intel. Refer to the appropriate platform design guidelines for implementation details. The FSB utilizes a split- transaction, deferred reply protocol and Source- Synchronous Transfer (SST) of address and data to improve performance. The processor transfers data four times per bus clock (4. X data transfer rate, as in AGP 4. X). Along with the 4. X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a `double- clocked' or a 2. X address bus. In addition, the Request Phase completes in one clock cycle. The FSB is also used to deliver interrupts. Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages. Section 2. 1 contains the electrical specifications of the FSB while implementation details are fully described in the appropriate platform design guidelines (refer to Section 1. Terminology A `#' symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the `#' symbol implies that the signal is inverted. Commonly used terms are explained here for clarification: 1. Dual- Core Intel. See the LGA7. 71 LGA7. Socket Design Guidelines for details regarding this socket. L2 cache and system bus interface are shared between the two cores on the die. All AC timing and signal integrity specifications are at the pads of the processor core. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. The values are only estimates and actual specifications for future processors may differ. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.
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